#Build: Synplify Pro I-2013.09M-SP1 , Build 034R, Jan 17 2014 #install: C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1 #OS: Windows 7 6.1 #Hostname: W764-UPPALAPATI #Implementation: synthesis $ Start of Compile #Fri Apr 18 09:30:48 2014 Synopsys Verilog Compiler, version comp201309rcp1, Build 078R, built Jan 14 2014 @N: : | Running in 64-bit mode Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\generic\igloo2.v" @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\umr_capim.v" @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\scemi_objects.v" @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\scemi_pipes.svh" @I::"C:\Microsemi\Libero_v11.3\Synopsys\synplify_I201309MSP1\lib\vlog\hypermods.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_top\FCCC_0\IGLOO2_Oversampling_top_FCCC_0_FCCC.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling\CCC_0\IGLOO2_Oversampling_CCC_0_FCCC.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreConfigMaster\2.0.101\rtl\vlog\core\coreconfigmaster.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreConfigP\5.0.101\rtl\vlog\core\coreconfigp.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreResetP\5.1.100\rtl\vlog\core\coreresetp.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\Actel\SgCore\OSC\1.0.100\osc_comps.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling\FABOSC_0\IGLOO2_Oversampling_FABOSC_0_OSC.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_HPMS\IGLOO2_Oversampling_HPMS_syn.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_HPMS\IGLOO2_Oversampling_HPMS.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_addrdec.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_defaultslavesm.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_masterstage.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavearbiter.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_slavestage.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite_matrix4x16.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\Actel\DirectCore\CoreAHBLite\5.0.100\rtl\vlog\core\coreahblite.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling\IGLOO2_Oversampling.v" @I::"C:\Microsemi\IGLOO2_Oversampling\hdl\Downsampler_Rx.v" @I::"C:\Microsemi\IGLOO2_Oversampling\hdl\PRBS_GenCheck.v" @I::"C:\Microsemi\IGLOO2_Oversampling\hdl\rx_data_aligner.v" @I::"C:\Microsemi\IGLOO2_Oversampling\hdl\receive_control.v" @I::"C:\Microsemi\IGLOO2_Oversampling\hdl\receive_buffer_top.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\Receiver\Receiver.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_top\SERDES_IF_0\IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF_syn.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_top\SERDES_IF_0\IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF.v" @I::"C:\Microsemi\IGLOO2_Oversampling\hdl\FIFO_PRBS.v" @I::"C:\Microsemi\IGLOO2_Oversampling\hdl\Replicator_Tx.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\Transmitter\Transmitter.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\Clock_gen.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\Tx_async.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\Rx_async.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\fifo_256x8_smartfusion2.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\COREUART_0\rtl\vlog\core\CoreUART.v" @I::"C:\Microsemi\IGLOO2_Oversampling\hdl\FabUART.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\UART_INTERFACE\UART_INTERFACE.v" @I::"C:\Microsemi\IGLOO2_Oversampling\component\work\IGLOO2_Oversampling_top\IGLOO2_Oversampling_top.v" @W:CG775 : coreahblite.v(32) | Found Component CoreAHBLite in library COREAHBLITE_LIB Verilog syntax check successful! Selecting top level module IGLOO2_Oversampling_top @N:CG364 : igloo2.v(362) | Synthesizing module CLKINT @N:CG364 : igloo2.v(371) | Synthesizing module VCC @N:CG364 : igloo2.v(367) | Synthesizing module GND @N:CG364 : igloo2.v(722) | Synthesizing module CCC @N:CG364 : IGLOO2_Oversampling_top_FCCC_0_FCCC.v(5) | Synthesizing module IGLOO2_Oversampling_top_FCCC_0_FCCC @N:CG364 : IGLOO2_Oversampling_CCC_0_FCCC.v(5) | Synthesizing module IGLOO2_Oversampling_CCC_0_FCCC @N:CG364 : coreconfigmaster.v(24) | Synthesizing module CoreConfigMaster DATA_LOCATION=32'b00000000000000111110100000000000 ADDR_SYSREG_SOFT_RESET=32'b01000000000000111000000001001000 ADDR_SYSREG_ENVM_BUSY=32'b01000000000000111000000101011000 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 S7=32'b00000000000000000000000000000111 S8=32'b00000000000000000000000000001000 S9=32'b00000000000000000000000000001001 S10=32'b00000000000000000000000000001010 S11=32'b00000000000000000000000000001011 S12=32'b00000000000000000000000000001100 S13=32'b00000000000000000000000000001101 S14=32'b00000000000000000000000000001110 P0=32'b00000000000000000000000000001111 P1=32'b00000000000000000000000000010000 P2=32'b00000000000000000000000000010001 P3=32'b00000000000000000000000000010010 P4=32'b00000000000000000000000000010011 P5=32'b00000000000000000000000000010100 P6=32'b00000000000000000000000000010101 OP_COPY=7'b0000000 Generated name = CoreConfigMaster_Z1 @W:CL190 : coreconfigmaster.v(541) | Optimizing register bit HTRANS[0] to a constant 0 @W:CL260 : coreconfigmaster.v(541) | Pruning register bit 0 of HTRANS[1:0] @W:CG775 : coreahblite.v(32) | Found Component CoreAHBLite in library COREAHBLITE_LIB @N:CG364 : coreahblite_addrdec.v(29) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z2 @N:CG364 : coreahblite_defaultslavesm.v(29) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM @N:CG364 : coreahblite_masterstage.v(31) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b10000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_65536_0_1_0 @N:CL177 : coreahblite_masterstage.v(629) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_addrdec.v(29) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011111 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z3 @N:CG364 : coreahblite_masterstage.v(31) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M_AHBSLOTENABLE=17'b00000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0 @N:CL177 : coreahblite_masterstage.v(629) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_slavearbiter.v(28) | Synthesizing module COREAHBLITE_SLAVEARBITER @N:CG364 : coreahblite_slavestage.v(30) | Synthesizing module COREAHBLITE_SLAVESTAGE @N:CG364 : coreahblite_matrix4x16.v(31) | Synthesizing module COREAHBLITE_MATRIX4X16 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC=16'b0000000001010101 M0_AHBSLOTENABLE=17'b10000000000000000 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 Generated name = COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0 @N:CG364 : coreahblite.v(32) | Synthesizing module CoreAHBLite FAMILY=6'b010011 MEMSPACE=3'b001 HADDR_SHG_CFG=1'b1 SC_0=1'b1 SC_1=1'b0 SC_2=1'b1 SC_3=1'b0 SC_4=1'b1 SC_5=1'b0 SC_6=1'b1 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b0 M0_AHBSLOT1ENABLE=1'b0 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b0 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b1 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b0 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 M0_AHBSLOTENABLE=17'b10000000000000000 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000001010101 Generated name = CoreAHBLite_Z4 @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000001 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z5 @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000001 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000001 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z6 @N:CG364 : coreresetp_pcie_hotreset.v(31) | Synthesizing module coreresetp_pcie_hotreset @W:CL169 : coreresetp.v(1562) | Pruning register count_ddr[13:0] @W:CL169 : coreresetp.v(1530) | Pruning register count_sdif3[12:0] @W:CL169 : coreresetp.v(1498) | Pruning register count_sdif2[12:0] @W:CL169 : coreresetp.v(1466) | Pruning register count_sdif1[12:0] @W:CL169 : coreresetp.v(1404) | Pruning register count_sdif1_enable_q1 @W:CL169 : coreresetp.v(1404) | Pruning register count_sdif2_enable_q1 @W:CL169 : coreresetp.v(1404) | Pruning register count_sdif3_enable_q1 @W:CL169 : coreresetp.v(1404) | Pruning register count_sdif1_enable_rcosc @W:CL169 : coreresetp.v(1404) | Pruning register count_sdif2_enable_rcosc @W:CL169 : coreresetp.v(1404) | Pruning register count_sdif3_enable_rcosc @W:CL169 : coreresetp.v(1404) | Pruning register count_ddr_enable_q1 @W:CL169 : coreresetp.v(1404) | Pruning register count_ddr_enable_rcosc @W:CL169 : coreresetp.v(1314) | Pruning register count_sdif3_enable @W:CL169 : coreresetp.v(1249) | Pruning register count_sdif2_enable @W:CL169 : coreresetp.v(1184) | Pruning register count_sdif1_enable @W:CL169 : coreresetp.v(1031) | Pruning register count_ddr_enable @N:CL177 : coreresetp.v(1337) | Sharing sequential element M3_RESET_N_int. @N:CL177 : coreresetp.v(936) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coreresetp.v(936) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coreresetp.v(936) | Sharing sequential element fpll_lock_q1. @W:CL190 : coreresetp.v(1382) | Optimizing register bit EXT_RESET_OUT_int to a constant 0 @W:CL169 : coreresetp.v(1031) | Pruning register release_ext_reset @W:CL169 : coreresetp.v(1382) | Pruning register EXT_RESET_OUT_int @W:CL169 : coreresetp.v(1382) | Pruning register sm2_state[2:0] @W:CL169 : coreresetp.v(756) | Pruning register sm2_areset_n_q1 @W:CL169 : coreresetp.v(756) | Pruning register sm2_areset_n_clk_base @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ @N:CG364 : IGLOO2_Oversampling_FABOSC_0_OSC.v(5) | Synthesizing module IGLOO2_Oversampling_FABOSC_0_OSC @N:CG364 : IGLOO2_Oversampling_HPMS_syn.v(5) | Synthesizing module MSS_010 @N:CG364 : IGLOO2_Oversampling_HPMS.v(9) | Synthesizing module IGLOO2_Oversampling_HPMS @N:CG364 : igloo2.v(713) | Synthesizing module SYSRESET @N:CG364 : IGLOO2_Oversampling.v(9) | Synthesizing module IGLOO2_Oversampling @N:CG364 : igloo2.v(156) | Synthesizing module AND3 @N:CG364 : Downsampler_Rx.v(29) | Synthesizing module Downsampler @N:CG364 : PRBS_GenCheck.v(26) | Synthesizing module prbs7_10 @N:CG179 : PRBS_GenCheck.v(193) | Removing redundant assignment @N:CG364 : rx_data_aligner.v(29) | Synthesizing module rx_data_aligner @N:CG179 : rx_data_aligner.v(506) | Removing redundant assignment @N:CG179 : rx_data_aligner.v(507) | Removing redundant assignment @N:CG364 : receive_control.v(29) | Synthesizing module receive_control @N:CG364 : receive_buffer_top.v(26) | Synthesizing module receive_buffer_top @N:CG364 : Receiver.v(9) | Synthesizing module Receiver @N:CG364 : IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF_syn.v(5) | Synthesizing module SERDESIF_0 @N:CG364 : IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF.v(5) | Synthesizing module IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF @N:CG364 : igloo2.v(126) | Synthesizing module AND2 @N:CG364 : FIFO_PRBS.v(23) | Synthesizing module FIFO_PRBS @W:CL190 : FIFO_PRBS.v(74) | Optimizing register bit reg_tx_val_out to a constant 1 @N:CG364 : Replicator_Tx.v(26) | Synthesizing module Replicator @N:CG364 : Transmitter.v(9) | Synthesizing module Transmitter @N:CG364 : Clock_gen.v(38) | Synthesizing module UART_INTERFACE_COREUART_0_Clock_gen BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 Generated name = UART_INTERFACE_COREUART_0_Clock_gen_0s @N:CG364 : Tx_async.v(31) | Synthesizing module UART_INTERFACE_COREUART_0_Tx_async TX_FIFO=32'b00000000000000000000000000000000 tx_idle=32'b00000000000000000000000000000000 tx_load=32'b00000000000000000000000000000001 start_bit=32'b00000000000000000000000000000010 tx_data_bits=32'b00000000000000000000000000000011 parity_bit=32'b00000000000000000000000000000100 tx_stop_bit=32'b00000000000000000000000000000101 delay_state=32'b00000000000000000000000000000110 Generated name = UART_INTERFACE_COREUART_0_Tx_async_0s_0s_1s_2s_3s_4s_5s_6s @N:CG179 : Tx_async.v(349) | Removing redundant assignment @W:CL190 : Tx_async.v(112) | Optimizing register bit fifo_read_en0 to a constant 1 @W:CL169 : Tx_async.v(112) | Pruning register fifo_read_en0 @N:CG364 : Rx_async.v(30) | Synthesizing module UART_INTERFACE_COREUART_0_Rx_async RX_FIFO=32'b00000000000000000000000000000000 receive_states_rx_idle=32'b00000000000000000000000000000000 receive_states_rx_data_bits=32'b00000000000000000000000000000001 receive_states_rx_stop_bit=32'b00000000000000000000000000000010 Generated name = UART_INTERFACE_COREUART_0_Rx_async_0s_0s_1s_2s @N:CG179 : Rx_async.v(243) | Removing redundant assignment @N:CL177 : Rx_async.v(459) | Sharing sequential element clear_framing_error_en. @N:CG364 : CoreUART.v(31) | Synthesizing module UART_INTERFACE_COREUART_0_COREUART TX_FIFO=32'b00000000000000000000000000000000 RX_FIFO=32'b00000000000000000000000000000000 RX_LEGACY_MODE=32'b00000000000000000000000000000000 FAMILY=32'b00000000000000000000000000010011 BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 Generated name = UART_INTERFACE_COREUART_0_COREUART_0s_0s_0s_19s_0s @N:CG179 : CoreUART.v(374) | Removing redundant assignment @W:CG360 : CoreUART.v(111) | No assignment to wire tx_dout_reg @W:CG360 : CoreUART.v(112) | No assignment to wire rx_dout @W:CG360 : CoreUART.v(118) | No assignment to wire fifo_empty_tx @W:CG360 : CoreUART.v(119) | No assignment to wire fifo_empty_rx @W:CG360 : CoreUART.v(123) | No assignment to wire fifo_full_tx @W:CG360 : CoreUART.v(124) | No assignment to wire fifo_full_rx @W:CG133 : CoreUART.v(135) | No assignment to data_ready @W:CL169 : CoreUART.v(360) | Pruning register overflow_reg @W:CL169 : CoreUART.v(335) | Pruning register rx_dout_reg_empty @W:CL169 : CoreUART.v(335) | Pruning register rx_dout_reg_empty_q @W:CL169 : CoreUART.v(320) | Pruning register rx_dout_reg[7:0] @W:CL169 : CoreUART.v(287) | Pruning register rx_state[1:0] @W:CL169 : CoreUART.v(272) | Pruning register clear_framing_error_reg @W:CL169 : CoreUART.v(272) | Pruning register clear_framing_error_reg0 @W:CL169 : CoreUART.v(257) | Pruning register clear_parity_reg @W:CL169 : CoreUART.v(257) | Pruning register clear_parity_reg0 @W:CL169 : CoreUART.v(154) | Pruning register fifo_write_tx @N:CG364 : FabUART.v(26) | Synthesizing module FabUART @W:CL190 : FabUART.v(91) | Optimizing register bit uart_data_out_t[6] to a constant 0 @W:CL190 : FabUART.v(91) | Optimizing register bit uart_data_out_t[7] to a constant 0 @W:CL279 : FabUART.v(91) | Pruning register bits 7 to 6 of uart_data_out_t[7:0] @N:CG364 : UART_INTERFACE.v(9) | Synthesizing module UART_INTERFACE @N:CG364 : IGLOO2_Oversampling_top.v(9) | Synthesizing module IGLOO2_Oversampling_top @N:CL201 : FabUART.v(91) | Trying to extract state machine for register state Extracted state machine for register state State machine has 18 reachable states with original encodings of: 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 @W:CL156 : CoreUART.v(111) | *Input tx_dout_reg[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : CoreUART.v(118) | *Input fifo_empty_tx to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible. @W:CL156 : CoreUART.v(123) | *Input fifo_full_tx to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible. @N:CL201 : Rx_async.v(255) | Trying to extract state machine for register rx_state Extracted state machine for register rx_state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL201 : Tx_async.v(112) | Trying to extract state machine for register xmit_state Extracted state machine for register xmit_state State machine has 6 reachable states with original encodings of: 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 00000000000000000000000000000100 00000000000000000000000000000101 @W:CL159 : Tx_async.v(43) | Input tx_dout_reg is unused @W:CL159 : Tx_async.v(44) | Input fifo_empty is unused @W:CL159 : Tx_async.v(45) | Input fifo_full is unused @W:CL159 : Clock_gen.v(50) | Input BAUD_VAL_FRACTION is unused @W:CL190 : FIFO_PRBS.v(74) | Optimizing register bit reg_tx_val_out to a constant 1 @N:CL201 : FIFO_PRBS.v(74) | Trying to extract state machine for register i Extracted state machine for register i State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL201 : receive_control.v(82) | Trying to extract state machine for register RC_FSM_state Extracted state machine for register RC_FSM_state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL201 : rx_data_aligner.v(349) | Trying to extract state machine for register DA_FSM_STATE Extracted state machine for register DA_FSM_STATE State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL201 : PRBS_GenCheck.v(92) | Trying to extract state machine for register tx_count Extracted state machine for register tx_count State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL201 : PRBS_GenCheck.v(92) | Trying to extract state machine for register rx_count Extracted state machine for register rx_count State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL247 : IGLOO2_Oversampling_HPMS.v(51) | Input port bit 0 of FIC_0_AHB_S_HTRANS[1:0] is unused @W:CL157 : IGLOO2_Oversampling_FABOSC_0_OSC.v(15) | *Output RCOSC_25_50MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : IGLOO2_Oversampling_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : IGLOO2_Oversampling_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : IGLOO2_Oversampling_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : IGLOO2_Oversampling_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible. @W:CL159 : IGLOO2_Oversampling_FABOSC_0_OSC.v(14) | Input XTL is unused @N:CL201 : coreresetp_pcie_hotreset.v(179) | Trying to extract state machine for register state Extracted state machine for register state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL247 : coreresetp_pcie_hotreset.v(36) | Input port bit 31 of prdata[31:0] is unused @W:CL246 : coreresetp_pcie_hotreset.v(36) | Input port bits 25 to 0 of prdata[31:0] are unused @N:CL177 : coreresetp.v(936) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coreresetp.v(936) | Sharing sequential element sdif2_spll_lock_q2. @N:CL177 : coreresetp.v(936) | Sharing sequential element fpll_lock_q2. @N:CL201 : coreresetp.v(1314) | Trying to extract state machine for register sdif3_state Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1249) | Trying to extract state machine for register sdif2_state Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1184) | Trying to extract state machine for register sdif1_state Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1119) | Trying to extract state machine for register sdif0_state Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1031) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused @W:CL159 : coreresetp.v(63) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coreresetp.v(67) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coreresetp.v(71) | Input SDIF3_SPLL_LOCK is unused @W:CL159 : coreresetp.v(88) | Input SDIF1_PSEL is unused @W:CL159 : coreresetp.v(89) | Input SDIF1_PWRITE is unused @W:CL159 : coreresetp.v(90) | Input SDIF1_PRDATA is unused @W:CL159 : coreresetp.v(91) | Input SDIF2_PSEL is unused @W:CL159 : coreresetp.v(92) | Input SDIF2_PWRITE is unused @W:CL159 : coreresetp.v(93) | Input SDIF2_PRDATA is unused @W:CL159 : coreresetp.v(94) | Input SDIF3_PSEL is unused @W:CL159 : coreresetp.v(95) | Input SDIF3_PWRITE is unused @W:CL159 : coreresetp.v(96) | Input SDIF3_PRDATA is unused @N:CL201 : coreconfigp.v(433) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL247 : coreahblite.v(128) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(139) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(150) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(161) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(171) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(184) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(197) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(210) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(223) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(236) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(249) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(262) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(275) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(288) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(301) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(314) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(327) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(340) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(353) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(366) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(379) | Input port bit 1 of HRESP_S16[1:0] is unused @W:CL159 : coreahblite.v(131) | Input HBURST_M0 is unused @W:CL159 : coreahblite.v(132) | Input HPROT_M0 is unused @W:CL159 : coreahblite.v(142) | Input HBURST_M1 is unused @W:CL159 : coreahblite.v(143) | Input HPROT_M1 is unused @W:CL159 : coreahblite.v(153) | Input HBURST_M2 is unused @W:CL159 : coreahblite.v(154) | Input HPROT_M2 is unused @W:CL159 : coreahblite.v(164) | Input HBURST_M3 is unused @W:CL159 : coreahblite.v(165) | Input HPROT_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(58) | Input HWDATA_M1 is unused @W:CL159 : coreahblite_matrix4x16.v(67) | Input HWDATA_M2 is unused @W:CL159 : coreahblite_matrix4x16.v(76) | Input HWDATA_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(80) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(81) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(82) | Input HRESP_S0 is unused @W:CL159 : coreahblite_matrix4x16.v(91) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(92) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(93) | Input HRESP_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(102) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(103) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(104) | Input HRESP_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(113) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(114) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(115) | Input HRESP_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(124) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(125) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(126) | Input HRESP_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(135) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(136) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(137) | Input HRESP_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(146) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(147) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(148) | Input HRESP_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(157) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(158) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(159) | Input HRESP_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(168) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(169) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(170) | Input HRESP_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(179) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(180) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(181) | Input HRESP_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(190) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(191) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(192) | Input HRESP_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(201) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(202) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(203) | Input HRESP_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(212) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(213) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(214) | Input HRESP_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(223) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(224) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(225) | Input HRESP_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(234) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(235) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(236) | Input HRESP_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(245) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(246) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(247) | Input HRESP_S15 is unused @W:CL246 : coreahblite_slavestage.v(46) | Input port bits 3 to 2 of MPREVDATASLAVEREADY[3:0] are unused @N:CL201 : coreahblite_slavearbiter.v(452) | Trying to extract state machine for register arbRegSMCurrentState Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @W:CL159 : coreahblite_masterstage.v(50) | Input SDATAREADY is unused @W:CL159 : coreahblite_masterstage.v(51) | Input SHRESP is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(86) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(87) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(88) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(89) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(90) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(91) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(92) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(93) | Input HREADYOUT_S16 is unused @W:CL246 : coreahblite_masterstage.v(50) | Input port bits 15 to 0 of SDATAREADY[16:0] are unused @W:CL246 : coreahblite_masterstage.v(51) | Input port bits 15 to 0 of SHRESP[16:0] are unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(86) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(87) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(88) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(89) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(90) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(91) | Input HREADYOUT_S15 is unused @N:CL201 : coreconfigmaster.v(541) | Trying to extract state machine for register state Extracted state machine for register state State machine has 21 reachable states with original encodings of: 00000 00001 00010 00011 00100 00101 00110 00111 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 @END At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 94MB peak: 121MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Fri Apr 18 09:30:51 2014 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09M-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Linked File: IGLOO2_Oversampling_top_scck.rpt Printing clock summary report in "C:\Microsemi\IGLOO2_Oversampling\synthesis\IGLOO2_Oversampling_top_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 112MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 112MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) @W:BN132 : coreahblite_matrix4x16.v(3567) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_15, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_14 @W:BN132 : coreahblite_matrix4x16.v(3522) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_14, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_13 @W:BN132 : coreahblite_matrix4x16.v(3477) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_13, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_12 @W:BN132 : coreahblite_matrix4x16.v(3432) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_12, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_11 @W:BN132 : coreahblite_matrix4x16.v(3387) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_11, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3297) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_9, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3252) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_8, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3207) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_7, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3162) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_6, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3117) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_5, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3072) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_4, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3027) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_3, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(2982) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_2, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3342) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_10, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_1 @W:BN132 : coreahblite_matrix4x16.v(2937) | Removing user instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_1, because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_0 @W:BN132 : coreresetp.v(1031) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.FDDR_CORE_RESET_N_int @N:BN362 : coreconfigp.v(447) | Removing sequential instance MDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(447) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(447) | Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(447) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(447) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : prbs_gencheck.v(92) | Removing sequential instance reg_tx_val of view:PrimLib.dffre(prim) in hierarchy view:work.prbs7_10_prbs7_10_0(verilog) because there are no references to its outputs @N:BN362 : prbs_gencheck.v(183) | Removing sequential instance reg_error_out of view:PrimLib.dffse(prim) in hierarchy view:work.prbs7_10_prbs7_10_0_0(verilog) because there are no references to its outputs @N:BN362 : prbs_gencheck.v(158) | Removing sequential instance reg_lock of view:PrimLib.dffre(prim) in hierarchy view:work.prbs7_10_prbs7_10_0_0(verilog) because there are no references to its outputs @N:BN362 : prbs_gencheck.v(205) | Removing sequential instance reg_lock_again of view:PrimLib.dffr(prim) in hierarchy view:work.prbs7_10_prbs7_10_0_0(verilog) because there are no references to its outputs @N:BN362 : rx_async.v(459) | Removing sequential instance fifo_write of view:PrimLib.dffs(prim) in hierarchy view:work.UART_INTERFACE_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs @N:BN362 : rx_async.v(459) | Removing sequential instance clear_parity_en_1 of view:PrimLib.dffr(prim) in hierarchy view:work.UART_INTERFACE_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs @N:BN362 : fabuart.v(91) | Removing sequential instance timer_switch_t of view:PrimLib.dffse(prim) in hierarchy view:work.FabUART(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2708) | Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_1(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2771) | Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_2(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2834) | Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0_0_1_0_masterstage_3(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2892) | Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1031) | Removing sequential instance USER_FAB_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1031) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1184) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1184) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1249) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1249) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1314) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1314) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : rx_async.v(198) | Removing sequential instance overflow of view:PrimLib.dffre(prim) in hierarchy view:work.UART_INTERFACE_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs @N:BN362 : rx_async.v(405) | Removing sequential instance parity_err of view:PrimLib.dffre(prim) in hierarchy view:work.UART_INTERFACE_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs @N:BN362 : rx_async.v(223) | Removing sequential instance framing_error of view:PrimLib.dffre(prim) in hierarchy view:work.UART_INTERFACE_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1119) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN115 : coreresetp.v(1642) | Removing instance genblk2\.sdif0_phr of view:work.coreresetp_pcie_hotreset(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1184) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1249) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1314) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(257) | Removing sequential instance sdif_core_reset_n of view:PrimLib.dffr(prim) in hierarchy view:work.coreresetp_pcie_hotreset(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1119) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(257) | Removing sequential instance sdif_core_reset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.coreresetp_pcie_hotreset(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(82) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_slavestage_0(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(784) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(798) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(812) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN115 : coreahblite_slavestage.v(90) | Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(784) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(798) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(812) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : rx_async.v(255) | Removing sequential instance overflow_int of view:PrimLib.dffre(prim) in hierarchy view:work.UART_INTERFACE_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs @N:BN362 : rx_async.v(255) | Removing sequential instance framing_error_int of view:PrimLib.dffre(prim) in hierarchy view:work.UART_INTERFACE_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs @N:BN362 : coreresetp_pcie_hotreset.v(179) | Removing sequential instance hot_reset_n of view:PrimLib.dffse(prim) in hierarchy view:work.coreresetp_pcie_hotreset(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(452) | Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter(verilog) because there are no references to its outputs syn_allowed_resources : blockrams=21 set on top level netlist IGLOO2_Oversampling_top Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ------------------------------------------------------------------------------------------------------------------------------------------- IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_5 IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_6 IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_3 IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_4 IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 =========================================================================================================================================== @W:MT530 : clock_gen.v(275) | Found inferred clock IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock which controls 116 sequential elements including UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[12:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : fifo_prbs.v(74) | Found inferred clock IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock which controls 103 sequential elements including Transmitter_0.FIFO_PRBS_0.reg_data_out[9:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : igloo2_oversampling_top_serdes_if_0_serdes_if.v(127) | Found inferred clock IGLOO2_Oversampling_top_FCCC_0_FCCC|GL1_net_inferred_clock which controls 0 sequential elements including SERDES_IF_0.SERDESIF_INST. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreconfigp.v(433) | Found inferred clock IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock which controls 107 sequential elements including IGLOO2_Oversampling_0.CORECONFIGP_0.FIC_2_APB_M_PREADY. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : downsampler_rx.v(59) | Found inferred clock IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock which controls 299 sequential elements including Receiver_0.Downsampler_0.reg_check[9:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreconfigmaster.v(541) | Found inferred clock IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock which controls 480 sequential elements including IGLOO2_Oversampling_0.ConfigMaster_0.state[20:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(1434) | Found inferred clock IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock which controls 30 sequential elements including IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[12:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\Microsemi\IGLOO2_Oversampling\synthesis\IGLOO2_Oversampling_top.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 77MB peak: 143MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Apr 18 09:30:54 2014 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1154R, Built Jan 20 2014 10:24:19 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2013.09M-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 140MB) @W:MO111 : igloo2_oversampling_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module IGLOO2_Oversampling_FABOSC_0_OSC) @W:MO111 : igloo2_oversampling_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module IGLOO2_Oversampling_FABOSC_0_OSC) @W:MO111 : igloo2_oversampling_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module IGLOO2_Oversampling_FABOSC_0_OSC) @W:MO111 : igloo2_oversampling_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module IGLOO2_Oversampling_FABOSC_0_OSC) @W:MO111 : igloo2_oversampling_fabosc_0_osc.v(15) | Tristate driver RCOSC_25_50MHZ_CCC on net RCOSC_25_50MHZ_CCC has its enable tied to GND (module IGLOO2_Oversampling_FABOSC_0_OSC) @W:MO171 : fifo_prbs.v(74) | Sequential instance Transmitter_0.FIFO_PRBS_0.reg_tx_val_out reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(668) | Sequential instance IGLOO2_Oversampling_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(687) | Sequential instance IGLOO2_Oversampling_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(706) | Sequential instance IGLOO2_Oversampling_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(668) | Sequential instance IGLOO2_Oversampling_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(687) | Sequential instance IGLOO2_Oversampling_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(706) | Sequential instance IGLOO2_Oversampling_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(649) | Sequential instance IGLOO2_Oversampling_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(668) | Sequential instance IGLOO2_Oversampling_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(687) | Sequential instance IGLOO2_Oversampling_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(706) | Sequential instance IGLOO2_Oversampling_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(742) | Sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @N:BN362 : prbs_gencheck.v(92) | Removing sequential instance tx_count[2:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.prbs7_10_prbs7_10_0(verilog) because there are no references to its outputs @N:BN362 : prbs_gencheck.v(92) | Removing sequential instance rx_count[2:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.prbs7_10_prbs7_10_0_0(verilog) because there are no references to its outputs @W:BN132 : coreresetp.v(936) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sdif3_spll_lock_q1, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.sdif0_spll_lock_q1 @W:BN132 : coreresetp.v(936) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sdif3_spll_lock_q2, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.sdif0_spll_lock_q2 @W:BN132 : coreresetp.v(742) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sm1_areset_n_clk_base, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.SDIF0_PERST_N_q2 @W:BN132 : coreresetp.v(871) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sdif2_areset_n_rcosc_q1, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(885) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sdif3_areset_n_rcosc_q1, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(829) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sm0_areset_n_rcosc_q1, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(885) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sdif3_areset_n_rcosc, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.sm0_areset_n_rcosc @W:BN132 : coreresetp.v(871) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sdif2_areset_n_rcosc, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.sm0_areset_n_rcosc @W:BN132 : coreresetp.v(857) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sdif1_areset_n_rcosc, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.sm0_areset_n_rcosc @W:BN132 : coreresetp.v(1530) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.release_sdif3_core, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.ddr_ready @W:BN132 : coreresetp.v(1498) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.release_sdif2_core, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.ddr_ready @W:BN132 : coreresetp.v(1466) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.release_sdif1_core, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.ddr_ready @W:BN132 : coreresetp.v(1595) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.release_sdif2_core_q1, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.release_sdif1_core_q1 @W:BN132 : coreresetp.v(1595) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.release_sdif3_core_q1, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.release_sdif1_core_q1 @W:BN132 : coreresetp.v(1595) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.release_sdif1_core_q1, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.ddr_ready_q1 @W:BN132 : coreresetp.v(1595) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.release_sdif3_core_clk_base, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.release_sdif2_core_clk_base @W:BN132 : coreresetp.v(1595) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.release_sdif2_core_clk_base, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.release_sdif1_core_clk_base @W:BN132 : coreresetp.v(1595) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.release_sdif1_core_clk_base, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.ddr_ready_clk_base Available hyper_sources - for debug and ip models None Found @W:MO129 : coreresetp.v(649) | Sequential instance IGLOO2_Oversampling_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO129 : coreresetp.v(1337) | Sequential instance IGLOO2_Oversampling_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation @W:MO129 : coreresetp.v(649) | Sequential instance IGLOO2_Oversampling_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation @W:BN132 : coreresetp.v(857) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sdif1_areset_n_rcosc_q1, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(728) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sm0_areset_n_q1, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.sdif0_areset_n_q1 @W:BN132 : coreresetp.v(843) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sdif0_areset_n_rcosc, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.sm0_areset_n_rcosc @W:BN132 : coreresetp.v(770) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sdif0_areset_n_clk_base, because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.sm0_areset_n_clk_base @N:BN362 : prbs_gencheck.v(183) | Removing sequential instance reg_error[5:0] of view:PrimLib.dffr(prim) in hierarchy view:work.prbs7_10_prbs7_10_0_0(verilog) because there are no references to its outputs @N:BN362 : rx_async.v(379) | Removing sequential instance rx_parity_calc of view:PrimLib.dffre(prim) in hierarchy view:work.UART_INTERFACE_COREUART_0_Rx_async_0s_0s_1s_2s(verilog) because there are no references to its outputs @N:BN362 : fabuart.v(91) | Removing sequential instance switch_t of view:PrimLib.dffre(prim) in hierarchy view:work.FabUART(verilog) because there are no references to its outputs @W:BN132 : coreresetp.v(1031) | Removing sequential instance IGLOO2_Oversampling_0.CORERESETP_0.sm0_state[3:0], because it is equivalent to instance IGLOO2_Oversampling_0.CORERESETP_0.sdif0_state[3:0] Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB) @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(82) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[3] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(82) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[2] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(82) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg[1] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(233) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(233) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(233) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[4] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(233) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[6] in hierarchy view:work.IGLOO2_Oversampling(verilog) because there are no references to its outputs @W:BN132 : coreahblite_masterstage.v(167) | Removing instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31], because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] Encoding state machine state[20:0] (view:work.CoreConfigMaster_Z1(verilog)) original code -> new code 00000 -> 000000000000000000001 00001 -> 000000000000000000010 00010 -> 000000000000000000100 00011 -> 000000000000000001000 00100 -> 000000000000000010000 00101 -> 000000000000000100000 00110 -> 000000000000001000000 00111 -> 000000000000010000000 01001 -> 000000000000100000000 01010 -> 000000000001000000000 01011 -> 000000000010000000000 01100 -> 000000000100000000000 01101 -> 000000001000000000000 01110 -> 000000010000000000000 01111 -> 000000100000000000000 10000 -> 000001000000000000000 10001 -> 000010000000000000000 10010 -> 000100000000000000000 10011 -> 001000000000000000000 10100 -> 010000000000000000000 10101 -> 100000000000000000000 @N: : coreconfigmaster.v(541) | Found counter in view:work.CoreConfigMaster_Z1(verilog) inst pause_count[4:0] @N:MF179 : coreconfigmaster.v(509) | Found 32 bit by 32 bit '==' comparator, 'd_state128' @N:BN362 : coreconfigmaster.v(541) | Removing sequential instance HSIZE[2] in hierarchy view:work.CoreConfigMaster_Z1(verilog) because there are no references to its outputs @A:BN291 : coreconfigmaster.v(541) | Boundary register HSIZE[2] packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_slave_arbiter_0(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(452) | Register bit arbRegSMCurrentState[12] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(452) | Register bit arbRegSMCurrentState[8] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(452) | Register bit arbRegSMCurrentState[4] is always 0, optimizing ... Encoding state machine state[2:0] (view:work.CoreConfigP_Z5(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : coreconfigp.v(241) | Removing sequential instance paddr[16] in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs Encoding state machine sdif0_state[3:0] (view:work.CoreResetP_Z6(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 @N: : coreresetp.v(1434) | Found counter in view:work.CoreResetP_Z6(verilog) inst count_sdif0[12:0] Encoding state machine rx_count[2:0] (view:work.prbs7_10_prbs7_10_0(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : prbs_gencheck.v(92) | Removing sequential instance LFSR[8] in hierarchy view:work.prbs7_10_prbs7_10_0(verilog) because there are no references to its outputs @N:BN362 : prbs_gencheck.v(92) | Removing sequential instance LFSR[9] in hierarchy view:work.prbs7_10_prbs7_10_0(verilog) because there are no references to its outputs @N:BN362 : prbs_gencheck.v(92) | Removing sequential instance LFSR[10] in hierarchy view:work.prbs7_10_prbs7_10_0(verilog) because there are no references to its outputs @N: : prbs_gencheck.v(183) | Found counter in view:work.prbs7_10_prbs7_10_0(verilog) inst reg_error[5:0] @N:MF179 : prbs_gencheck.v(188) | Found 10 bit by 10 bit '==' comparator, 'un1_data_in' Encoding state machine DA_FSM_STATE[3:0] (view:work.rx_data_aligner(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Encoding state machine RC_FSM_state[2:0] (view:work.receive_control(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine i[2:0] (view:work.FIFO_PRBS(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine tx_count[2:0] (view:work.prbs7_10_prbs7_10_0_0(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:BN132 : coreuart.v(154) | Removing instance UART_INTERFACE_0.COREUART_0.tx_hold_reg[7], because it is equivalent to instance UART_INTERFACE_0.COREUART_0.tx_hold_reg[6] @N:BN362 : coreuart.v(154) | Removing sequential instance tx_hold_reg[6] in hierarchy view:work.UART_INTERFACE_COREUART_0_COREUART_0s_0s_0s_19s_0s(verilog) because there are no references to its outputs @N: : clock_gen.v(275) | Found counter in view:work.UART_INTERFACE_COREUART_0_Clock_gen_0s(verilog) inst genblk1\.baud_cntr[12:0] Encoding state machine xmit_state[5:0] (view:work.UART_INTERFACE_COREUART_0_Tx_async_0s_0s_1s_2s_3s_4s_5s_6s(verilog)) original code -> new code 00000000000000000000000000000000 -> 000001 00000000000000000000000000000001 -> 000010 00000000000000000000000000000010 -> 000100 00000000000000000000000000000011 -> 001000 00000000000000000000000000000100 -> 010000 00000000000000000000000000000101 -> 100000 @W:MO160 : tx_async.v(112) | Register bit xmit_state[4] is always 0, optimizing ... @N:BN362 : tx_async.v(332) | Removing sequential instance tx_parity in hierarchy view:work.UART_INTERFACE_COREUART_0_Tx_async_0s_0s_1s_2s_3s_4s_5s_6s(verilog) because there are no references to its outputs Encoding state machine rx_state[2:0] (view:work.UART_INTERFACE_COREUART_0_Rx_async_0s_0s_1s_2s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine state[17:0] (view:work.FabUART(verilog)) original code -> new code 00000 -> 000000000000000001 00001 -> 000000000000000010 00010 -> 000000000000000100 00011 -> 000000000000001000 00100 -> 000000000000010000 00101 -> 000000000000100000 00110 -> 000000000001000000 00111 -> 000000000010000000 01000 -> 000000000100000000 01001 -> 000000001000000000 01010 -> 000000010000000000 01011 -> 000000100000000000 01100 -> 000001000000000000 01101 -> 000010000000000000 01110 -> 000100000000000000 01111 -> 001000000000000000 10000 -> 010000000000000000 10001 -> 100000000000000000 @W:BN132 : tx_async.v(112) | Removing instance UART_INTERFACE_0.COREUART_0.make_TX.tx_byte[7], because it is equivalent to instance UART_INTERFACE_0.COREUART_0.make_TX.tx_byte[6] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[28], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[27] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[29], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[27] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[25], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[24] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[26], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[24] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[22], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[21] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[23], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[21] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[20], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[19] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[19], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[18] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[16], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[15] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[17], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[15] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[13], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[12] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[14], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[12] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[10], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[9] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[11], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[9] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[7], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[6] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[8], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[6] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[4], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[3] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[5], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[3] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[1], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[0] @W:BN132 : fifo_prbs.v(74) | Removing instance Transmitter_0.FIFO_PRBS_0.data[2], because it is equivalent to instance Transmitter_0.FIFO_PRBS_0.data[0] @N:BN362 : coreahblite_masterstage.v(167) | Removing sequential instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] in hierarchy view:work.IGLOO2_Oversampling_top(verilog) because there are no references to its outputs @N:BN362 : tx_async.v(112) | Removing sequential instance UART_INTERFACE_0.COREUART_0.make_TX.tx_byte[6] in hierarchy view:work.IGLOO2_Oversampling_top(verilog) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 154MB peak: 155MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 150MB peak: 156MB) @N:BN362 : rx_async.v(335) | Removing sequential instance UART_INTERFACE_0.COREUART_0.make_RX.rx_shift[8] in hierarchy view:work.IGLOO2_Oversampling_top(verilog) because there are no references to its outputs Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 156MB) @W:BN132 : coreahblite_slavearbiter.v(452) | Removing instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[7], because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11] @W:BN132 : coreahblite_slavearbiter.v(452) | Removing instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[15], because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11] @W:BN132 : coreahblite_slavearbiter.v(452) | Removing instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[14], because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6] @W:BN132 : coreahblite_slavearbiter.v(452) | Removing instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[10], because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6] @N:BN362 : coreahblite_slavearbiter.v(452) | Removing sequential instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[11] in hierarchy view:work.IGLOO2_Oversampling_top(verilog) because there are no references to its outputs @N:FX404 : coreconfigmaster.v(147) | Found addmux in view:work.IGLOO2_Oversampling_top(verilog) inst IGLOO2_Oversampling_0.ConfigMaster_0.d_bytecount_0[15:0] from IGLOO2_Oversampling_0.ConfigMaster_0.un1_bytecount_16[15:0] Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 156MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 156MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 156MB) @N:BN362 : coreahblite_slavearbiter.v(452) | Removing sequential instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6] in hierarchy view:work.IGLOO2_Oversampling_top(verilog) because there are no references to its outputs @W:BN132 : coreahblite_slavearbiter.v(452) | Removing instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[9], because it is equivalent to instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5] @N:BN362 : coreahblite_slavearbiter.v(452) | Removing sequential instance IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5] in hierarchy view:work.IGLOO2_Oversampling_top(verilog) because there are no references to its outputs Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 150MB peak: 156MB) Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 163MB peak: 165MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:02s -25.38ns 1092 / 1009 2 0h:00m:02s -24.54ns 1092 / 1009 3 0h:00m:02s -24.54ns 1092 / 1009 ------------------------------------------------------------ @N:FX271 : coreconfigmaster.v(541) | Instance "IGLOO2_Oversampling_0.ConfigMaster_0.HADDR[0]" with 5 loads replicated 1 times to improve timing Timing driven replication report Added 1 Registers via timing driven replication Added 1 LUTs via timing driven replication Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:02s -15.06ns 1104 / 1010 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:02s -15.06ns 1104 / 1010 ------------------------------------------------------------ @N:FP130 : | Promoting Net SERDES_IF_0_EPCS_1_TX_CLK on CLKINT I_134 @N:FP130 : | Promoting Net IGLOO2_Oversampling_0_INIT_APB_S_PCLK on CLKINT I_135 @N:FP130 : | Promoting Net IGLOO2_Oversampling_0_INIT_APB_S_PRESET_N on CLKINT I_136 @N:FP130 : | Promoting Net SERDES_IF_0_EPCS_1_RX_CLK on CLKINT I_137 @N:FP130 : | Promoting Net IGLOO2_Oversampling_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT I_138 @N:FP130 : | Promoting Net IGLOO2_Oversampling_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_139 @N:FP130 : | Promoting Net Receiver_0.AND3_0_Y on CLKINT I_140 @N:FP130 : | Promoting Net Transmitter_0.EPCS_TX_RESET_net_0 on CLKINT I_141 @N:FP130 : | Promoting Net FCCC_0_LOCK on CLKINT I_142 @N:FP130 : | Promoting Net IGLOO2_Oversampling_0.HPMS_READY_i_0_i on CLKINT I_143 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 152MB peak: 165MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 152MB peak: 165MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 6 non-gated/non-generated clock tree(s) driving 907 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 106 clock pin(s) of sequential element(s) 0 instances converted, 106 sequential instances remain driven by gated/generated clocks ===================================================================== Non-Gated/Non-Generated Clocks ====================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0002 SERDES_IF_0.SERDESIF_INST SERDESIF_0 289 Receiver_0.prbs7_10_0.reg_error[5] ClockId0003 SERDES_IF_0.SERDESIF_INST SERDESIF_0 69 Transmitter_0.Replicator_0.reg_tx_val_out ClockId0004 IGLOO2_Oversampling_0.CCC_0.GL0_INST CLKINT 423 IGLOO2_Oversampling_0.IGLOO2_Oversampling_HPMS_0.MSS_ADLIB_INST ClockId0005 FCCC_0.GL0_INST CLKINT 106 UART_INTERFACE_0.FabUART_0.state[14] ClockId0006 IGLOO2_Oversampling_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB RCOSC_25_50MHZ_FAB 19 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[12] ClockId0007 FCCC_0.GL1_INST CLKINT 1 SERDES_IF_0.SERDESIF_INST =========================================================================================================================================================================== ============================================================================================================== Gated/Generated Clocks =============================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 IGLOO2_Oversampling_0.IGLOO2_Oversampling_HPMS_0.MSS_ADLIB_INST MSS_010 106 IGLOO2_Oversampling_0.CORECONFIGP_0.INIT_DONE_q3 No generated or derived clock directive on output of sequential instance ===================================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base C:\Microsemi\IGLOO2_Oversampling\synthesis\IGLOO2_Oversampling_top.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 147MB peak: 165MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF I-2013.09M-SP1 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 148MB peak: 165MB) @W:MT246 : igloo2_oversampling.v(1003) | Blackbox SYSRESET is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : igloo2_oversampling_ccc_0_fccc.v(23) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SERDES_IF_0.EPCS_1_RX_CLK" @W:MT420 : | Found inferred clock IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:SERDES_IF_0.EPCS_1_TX_CLK" @W:MT420 : | Found inferred clock IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:IGLOO2_Oversampling_0.IGLOO2_Oversampling_HPMS_0.FIC_2_APB_M_PCLK" @W:MT420 : | Found inferred clock IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:IGLOO2_Oversampling_0.FABOSC_0.N_RCOSC_25_50MHZ_CLKOUT" @W:MT420 : | Found inferred clock IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:IGLOO2_Oversampling_0.CCC_0.GL0_net" @W:MT420 : | Found inferred clock IGLOO2_Oversampling_top_FCCC_0_FCCC|GL1_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_0.GL1_net" @W:MT420 : | Found inferred clock IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_0.GL0_net" ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Apr 18 09:31:00 2014 # Top view: IGLOO2_Oversampling_top Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 0.862 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 110.5 MHz 10.000 9.053 0.947 inferred Inferred_clkgroup_5 IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock 100.0 MHz 408.6 MHz 10.000 2.447 7.553 inferred Inferred_clkgroup_6 IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 120.8 MHz 10.000 8.277 0.862 inferred Inferred_clkgroup_3 IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 219.4 MHz 10.000 4.557 5.443 inferred Inferred_clkgroup_0 IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock 100.0 MHz 148.4 MHz 10.000 6.738 3.262 inferred Inferred_clkgroup_4 IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock 100.0 MHz 400.7 MHz 10.000 2.496 7.504 inferred Inferred_clkgroup_1 System 100.0 MHz NA 10.000 NA NA system system_clkgroup ================================================================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock | 10.000 5.443 | No paths - | No paths - | No paths - IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock | 10.000 7.504 | No paths - | No paths - | No paths - IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock | 10.000 2.983 | No paths - | 5.000 2.951 | 5.000 0.862 IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock | 10.000 3.262 | No paths - | No paths - | No paths - IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 0.947 | No paths - | No paths - | No paths - IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock | Diff grp - | No paths - | No paths - | No paths - IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock | 10.000 7.553 | No paths - | No paths - | No paths - ============================================================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- IGLOO2_Oversampling_0.IGLOO2_Oversampling_HPMS_0.MSS_ADLIB_INST IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock MSS_010 F_FM0_READYOUT CoreAHBLite_0_AHBmslave16_HREADY 2.910 0.947 IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[3] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[3] 0.076 1.941 IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[10] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[10] 0.076 2.008 IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[8] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[8] 0.076 2.155 IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[11] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[11] 0.076 2.223 IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[9] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[9] 0.076 2.227 IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[13] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[13] 0.076 2.264 IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[12] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[12] 0.076 2.294 IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[1] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[1] 0.076 2.319 IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[15] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[15] 0.076 2.332 ================================================================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- IGLOO2_Oversampling_0.ConfigMaster_0.HADDR[4] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE D d_HADDR[4] 9.778 0.947 IGLOO2_Oversampling_0.ConfigMaster_0.HADDR[0] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE D d_HADDR[0] 9.848 1.179 IGLOO2_Oversampling_0.ConfigMaster_0.HADDR_fast[0] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE D d_HADDR_fast[0] 9.848 1.179 IGLOO2_Oversampling_0.ConfigMaster_0.HADDR[15] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE D d_HADDR_0_iv_i_0[15] 9.778 1.198 IGLOO2_Oversampling_0.ConfigMaster_0.HADDR[16] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE D d_HADDR_0_iv_i_0[16] 9.778 1.198 IGLOO2_Oversampling_0.ConfigMaster_0.HADDR[17] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE D d_HADDR_0_iv_i_0[17] 9.778 1.198 IGLOO2_Oversampling_0.ConfigMaster_0.HADDR[31] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE D d_HADDR[31] 9.778 1.217 IGLOO2_Oversampling_0.ConfigMaster_0.HADDR[1] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE D d_HADDR[1] 9.848 1.244 IGLOO2_Oversampling_0.ConfigMaster_0.HADDR[2] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE D d_HADDR[2] 9.848 1.244 IGLOO2_Oversampling_0.ConfigMaster_0.HADDR[5] IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock SLE D d_HADDR[5] 9.848 1.244 ============================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 8.831 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.947 Number of logic level(s): 6 Starting point: IGLOO2_Oversampling_0.IGLOO2_Oversampling_HPMS_0.MSS_ADLIB_INST / F_FM0_READYOUT Ending point: IGLOO2_Oversampling_0.ConfigMaster_0.HADDR[4] / D The start point is clocked by IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by IGLOO2_Oversampling_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- IGLOO2_Oversampling_0.IGLOO2_Oversampling_HPMS_0.MSS_ADLIB_INST MSS_010 F_FM0_READYOUT Out 2.910 2.910 - CoreAHBLite_0_AHBmslave16_HREADY Net - - 0.989 - 11 IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg_RNI7TTB1[0] CFG4 C In - 3.899 - IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.slavestage_16.masterDataInProg_RNI7TTB1[0] CFG4 Y Out 0.196 4.095 - d_bytecount_3_sqmuxa_1 Net - - 0.761 - 12 IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv CFG2 A In - 4.856 - IGLOO2_Oversampling_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv CFG2 Y Out 0.076 4.932 - HREADY_i_3 Net - - 0.914 - 32 IGLOO2_Oversampling_0.ConfigMaster_0.un1_d_HWRITE_1_sqmuxa CFG4 D In - 5.846 - IGLOO2_Oversampling_0.ConfigMaster_0.un1_d_HWRITE_1_sqmuxa CFG4 Y Out 0.384 6.230 - un1_d_HWRITE_1_sqmuxa Net - - 0.914 - 32 IGLOO2_Oversampling_0.ConfigMaster_0.d_HADDR_0_iv_2_RNO[4] CFG2 A In - 7.144 - IGLOO2_Oversampling_0.ConfigMaster_0.d_HADDR_0_iv_2_RNO[4] CFG2 Y Out 0.067 7.212 - un32_d_HADDR_m[4] Net - - 0.483 - 1 IGLOO2_Oversampling_0.ConfigMaster_0.d_HADDR_0_iv_2[4] CFG4 B In - 7.695 - IGLOO2_Oversampling_0.ConfigMaster_0.d_HADDR_0_iv_2[4] CFG4 Y Out 0.143 7.838 - d_HADDR_0_iv_2[4] Net - - 0.483 - 1 IGLOO2_Oversampling_0.ConfigMaster_0.d_HADDR_0_iv[4] CFG4 D In - 8.321 - IGLOO2_Oversampling_0.ConfigMaster_0.d_HADDR_0_iv[4] CFG4 Y Out 0.372 8.693 - d_HADDR[4] Net - - 0.138 - 1 IGLOO2_Oversampling_0.ConfigMaster_0.HADDR[4] SLE D In - 8.831 - ===================================================================================================================================================================== Total path delay (propagation time + setup) of 9.053 is 4.371(48.3%) logic and 4.683(51.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[0] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[0] 0.076 7.553 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[1] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[1] 0.094 7.746 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[2] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[2] 0.094 7.760 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[3] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[3] 0.094 7.774 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[4] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[4] 0.094 7.789 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[5] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[5] 0.094 7.803 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[6] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[6] 0.094 7.817 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[7] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[7] 0.094 7.831 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[8] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[8] 0.094 7.845 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[9] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_sdif0[9] 0.094 7.858 ======================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- IGLOO2_Oversampling_0.CORERESETP_0.release_sdif0_core IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE EN release_sdif0_core4 9.707 7.553 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[12] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[12] 9.778 7.681 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[11] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[11] 9.778 7.695 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[10] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[10] 9.778 7.709 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[9] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[9] 9.778 7.723 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[8] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[8] 9.778 7.738 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[7] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[7] 9.778 7.752 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[6] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[6] 9.778 7.766 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[5] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[5] 9.778 7.780 IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[4] IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_sdif0_s[4] 9.778 7.795 ================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.707 - Propagation time: 2.154 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.553 Number of logic level(s): 2 Starting point: IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[0] / Q Ending point: IGLOO2_Oversampling_0.CORERESETP_0.release_sdif0_core / EN The start point is clocked by IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock [rising] on pin CLK The end point is clocked by IGLOO2_Oversampling_FABOSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------- IGLOO2_Oversampling_0.CORERESETP_0.count_sdif0[0] SLE Q Out 0.076 0.076 - count_sdif0[0] Net - - 0.637 - 3 IGLOO2_Oversampling_0.CORERESETP_0.release_sdif0_core4_8 CFG4 D In - 0.714 - IGLOO2_Oversampling_0.CORERESETP_0.release_sdif0_core4_8 CFG4 Y Out 0.411 1.124 - release_sdif0_core4_8 Net - - 0.483 - 1 IGLOO2_Oversampling_0.CORERESETP_0.release_sdif0_core4 CFG4 D In - 1.607 - IGLOO2_Oversampling_0.CORERESETP_0.release_sdif0_core4 CFG4 Y Out 0.408 2.016 - release_sdif0_core4 Net - - 0.138 - 1 IGLOO2_Oversampling_0.CORERESETP_0.release_sdif0_core SLE EN In - 2.154 - ======================================================================================================================= Total path delay (propagation time + setup) of 2.447 is 1.189(48.6%) logic and 1.259(51.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ IGLOO2_Oversampling_0.CORECONFIGP_0.psel IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE Q psel 0.094 0.862 IGLOO2_Oversampling_0.CORECONFIGP_0.state[1] IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE Q state[1] 0.076 2.951 SERDES_IF_0.SERDESIF_INST IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_0 APB_PRDATA[7] IGLOO2_Oversampling_0_SDIF0_INIT_APB_PRDATA[7] 5.543 2.983 SERDES_IF_0.SERDESIF_INST IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_0 APB_PRDATA[0] IGLOO2_Oversampling_0_SDIF0_INIT_APB_PRDATA[0] 5.106 3.381 IGLOO2_Oversampling_0.CORECONFIGP_0.SDIF0_PENABLE IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE Q IGLOO2_Oversampling_0_SDIF0_INIT_APB_PENABLE 0.094 3.382 SERDES_IF_0.SERDESIF_INST IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_0 APB_PRDATA[4] IGLOO2_Oversampling_0_SDIF0_INIT_APB_PRDATA[4] 5.102 3.424 SERDES_IF_0.SERDESIF_INST IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_0 APB_PRDATA[2] IGLOO2_Oversampling_0_SDIF0_INIT_APB_PRDATA[2] 5.047 3.479 SERDES_IF_0.SERDESIF_INST IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_0 APB_PRDATA[1] IGLOO2_Oversampling_0_SDIF0_INIT_APB_PRDATA[1] 5.041 3.485 SERDES_IF_0.SERDESIF_INST IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_0 APB_PRDATA[5] IGLOO2_Oversampling_0_SDIF0_INIT_APB_PRDATA[5] 5.041 3.485 SERDES_IF_0.SERDESIF_INST IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_0 APB_PRDATA[6] IGLOO2_Oversampling_0_SDIF0_INIT_APB_PRDATA[6] 5.035 3.491 ======================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- SERDES_IF_0.SERDESIF_INST IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SERDESIF_0 APB_PSEL IGLOO2_Oversampling_0_SDIF0_INIT_APB_PSELx 3.430 0.862 IGLOO2_Oversampling_0.CORECONFIGP_0.state[1] IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D state_ns[1] 4.778 1.718 IGLOO2_Oversampling_0.CORECONFIGP_0.FIC_2_APB_M_PREADY IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE EN N_71_i_0 4.707 1.822 IGLOO2_Oversampling_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[0] IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[0] 4.778 1.947 IGLOO2_Oversampling_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[15] IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[15] 4.778 1.947 IGLOO2_Oversampling_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[16] IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[16] 4.778 1.947 IGLOO2_Oversampling_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[17] IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[17] 4.778 1.947 IGLOO2_Oversampling_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[18] IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[18] 4.778 1.947 IGLOO2_Oversampling_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[19] IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[19] 4.778 1.947 IGLOO2_Oversampling_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[20] IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[20] 4.778 1.947 ========================================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 1.570 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.430 - Propagation time: 2.568 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.862 Number of logic level(s): 1 Starting point: IGLOO2_Oversampling_0.CORECONFIGP_0.psel / Q Ending point: SERDES_IF_0.SERDESIF_INST / APB_PSEL The start point is clocked by IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock [falling] on pin CLK The end point is clocked by IGLOO2_Oversampling_HPMS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin APB_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- IGLOO2_Oversampling_0.CORECONFIGP_0.psel SLE Q Out 0.094 0.094 - psel Net - - 1.294 - 20 IGLOO2_Oversampling_0.CORECONFIGP_0.R_SDIF0_PSEL_1_0_a2 CFG3 C In - 1.388 - IGLOO2_Oversampling_0.CORECONFIGP_0.R_SDIF0_PSEL_1_0_a2 CFG3 Y Out 0.182 1.570 - IGLOO2_Oversampling_0_SDIF0_INIT_APB_PSELx Net - - 0.998 - 36 SERDES_IF_0.SERDESIF_INST SERDESIF_0 APB_PSEL In - 2.568 - ================================================================================================================================ Total path delay (propagation time + setup) of 4.138 is 1.846(44.6%) logic and 2.292(55.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[8] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q baud_cntr[8] 0.076 5.443 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[5] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q baud_cntr[5] 0.076 5.513 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[9] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q baud_cntr[9] 0.094 5.636 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[0] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q baud_cntr[0] 0.076 5.654 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[10] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q baud_cntr[10] 0.094 5.703 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[6] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q baud_cntr[6] 0.076 5.728 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[11] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q baud_cntr[11] 0.094 5.746 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[7] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q baud_cntr[7] 0.076 5.800 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[12] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q baud_cntr[12] 0.076 5.837 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[1] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q baud_cntr[1] 0.094 5.847 ========================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[12] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE D baud_cntr_s[12] 9.778 5.443 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[11] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE D baud_cntr_s[11] 9.778 5.457 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[10] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE D baud_cntr_s[10] 9.778 5.471 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[9] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE D baud_cntr_s[9] 9.778 5.486 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[8] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE D baud_cntr_s[8] 9.778 5.500 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[7] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE D baud_cntr_s[7] 9.778 5.514 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[6] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE D baud_cntr_s[6] 9.778 5.528 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[1] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE D baud_cntr_s[1] 9.778 5.535 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[5] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE D baud_cntr_s[5] 9.778 5.541 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[4] IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE D baud_cntr_s[4] 9.778 5.554 ============================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 4.335 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 5.443 Number of logic level(s): 14 Starting point: UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[8] / Q Ending point: UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[12] / D The start point is clocked by IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK The end point is clocked by IGLOO2_Oversampling_top_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------- UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[8] SLE Q Out 0.076 0.076 - baud_cntr[8] Net - - 0.587 - 2 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.make_baud_cntr\.baud_cntr8_7 CFG4 D In - 0.663 - UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.make_baud_cntr\.baud_cntr8_7 CFG4 Y Out 0.411 1.073 - baud_cntr8_7 Net - - 0.548 - 2 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.make_baud_cntr\.baud_cntr8_1_RNI29NL1 ARI1 D In - 1.621 - UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.make_baud_cntr\.baud_cntr8_1_RNI29NL1 ARI1 Y Out 0.411 2.032 - baud_cntr8_1_RNI29NL1_Y Net - - 0.971 - 1 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIJLG04[1] ARI1 B In - 3.003 - UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIJLG04[1] ARI1 FCO Out 0.155 3.158 - baud_cntr_cry[1] Net - - 0.000 - 1 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIG40H4[2] ARI1 FCI In - 3.158 - UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIG40H4[2] ARI1 FCO Out 0.014 3.172 - baud_cntr_cry[2] Net - - 0.000 - 1 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIEKF15[3] ARI1 FCI In - 3.172 - UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIEKF15[3] ARI1 FCO Out 0.014 3.187 - baud_cntr_cry[3] Net - - 0.000 - 1 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNID5VH5[4] ARI1 FCI In - 3.187 - UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNID5VH5[4] ARI1 FCO Out 0.014 3.201 - baud_cntr_cry[4] Net - - 0.000 - 1 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIDNE26[5] ARI1 FCI In - 3.201 - UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIDNE26[5] ARI1 FCO Out 0.014 3.215 - baud_cntr_cry[5] Net - - 0.000 - 1 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIEAUI6[6] ARI1 FCI In - 3.215 - UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIEAUI6[6] ARI1 FCO Out 0.014 3.229 - baud_cntr_cry[6] Net - - 0.000 - 1 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIGUD37[7] ARI1 FCI In - 3.229 - UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIGUD37[7] ARI1 FCO Out 0.014 3.243 - baud_cntr_cry[7] Net - - 0.000 - 1 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIJJTJ7[8] ARI1 FCI In - 3.243 - UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIJJTJ7[8] ARI1 FCO Out 0.014 3.258 - baud_cntr_cry[8] Net - - 0.000 - 1 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIN9D48[9] ARI1 FCI In - 3.258 - UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIN9D48[9] ARI1 FCO Out 0.014 3.272 - baud_cntr_cry[9] Net - - 0.000 - 1 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNI3KTL8[10] ARI1 FCI In - 3.272 - UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNI3KTL8[10] ARI1 FCO Out 0.014 3.286 - baud_cntr_cry[10] Net - - 0.000 - 1 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIGVD79[11] ARI1 FCI In - 3.286 - UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNIGVD79[11] ARI1 FCO Out 0.014 3.300 - baud_cntr_cry[11] Net - - 0.000 - 1 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNO[12] ARI1 FCI In - 3.300 - UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr_RNO[12] ARI1 S Out 0.063 3.364 - baud_cntr_s[12] Net - - 0.971 - 1 UART_INTERFACE_0.COREUART_0.make_CLOCK_GEN.genblk1\.baud_cntr[12] SLE D In - 4.335 - ======================================================================================================================================================== Total path delay (propagation time + setup) of 4.557 is 1.480(32.5%) logic and 3.077(67.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Receiver_0.Downsampler_0.reg_data_out[2] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE Q Downsampler_0_data_out[2] 0.094 3.262 Receiver_0.prbs7_10_0.LFSR[7] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE Q LFSR[7] 0.094 3.265 Receiver_0.prbs7_10_0.LFSR[4] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE Q LFSR[4] 0.094 4.049 Receiver_0.prbs7_10_0.LFSR[5] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE Q LFSR[5] 0.094 4.105 Receiver_0.Downsampler_0.reg_data_out[7] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE Q Downsampler_0_data_out[7] 0.094 4.288 Receiver_0.prbs7_10_0.LFSR[6] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE Q LFSR[6] 0.094 4.680 Receiver_0.prbs7_10_0.LFSR[1] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE Q LFSR[1] 0.094 4.810 Receiver_0.Downsampler_0.reg_data_out[4] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE Q Downsampler_0_data_out[4] 0.094 5.021 Receiver_0.Downsampler_0.reg_data_out[3] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE Q Downsampler_0_data_out[3] 0.094 5.038 Receiver_0.prbs7_10_0.LFSR[2] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE Q LFSR[2] 0.094 5.131 ============================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Receiver_0.prbs7_10_0.lock_count[1] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE D N_14_i_1 9.778 3.262 Receiver_0.prbs7_10_0.reg_lock IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE EN un1_lock_count13_i_0 9.707 3.931 Receiver_0.prbs7_10_0.reg_error[0] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE EN N_179_i_0 9.707 3.999 Receiver_0.prbs7_10_0.reg_error[1] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE EN N_179_i_0 9.707 3.999 Receiver_0.prbs7_10_0.reg_error[2] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE EN N_179_i_0 9.707 3.999 Receiver_0.prbs7_10_0.reg_error[3] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE EN N_179_i_0 9.707 3.999 Receiver_0.prbs7_10_0.reg_error[4] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE EN N_179_i_0 9.707 3.999 Receiver_0.prbs7_10_0.reg_error[5] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE EN N_179_i_0 9.707 3.999 Receiver_0.prbs7_10_0.reg_error_out IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE EN N_179_i_0 9.707 3.999 Receiver_0.prbs7_10_0.lock_count[0] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock SLE D N_12_i_0 9.778 4.002 =================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 6.516 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 3.262 Number of logic level(s): 8 Starting point: Receiver_0.Downsampler_0.reg_data_out[2] / Q Ending point: Receiver_0.prbs7_10_0.lock_count[1] / D The start point is clocked by IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock [rising] on pin CLK The end point is clocked by IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_RX_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------- Receiver_0.Downsampler_0.reg_data_out[2] SLE Q Out 0.094 0.094 - Downsampler_0_data_out[2] Net - - 0.587 - 2 Receiver_0.prbs7_10_0.un1_data_in_2_0 CFG2 B In - 0.681 - Receiver_0.prbs7_10_0.un1_data_in_2_0 CFG2 Y Out 0.143 0.824 - un1_data_in_2_0 Net - - 0.483 - 1 Receiver_0.prbs7_10_0.un1_lock_count13_i_o2_0_2 CFG4 D In - 1.307 - Receiver_0.prbs7_10_0.un1_lock_count13_i_o2_0_2 CFG4 Y Out 0.411 1.718 - un1_lock_count13_i_o2_0_2 Net - - 0.483 - 1 Receiver_0.prbs7_10_0.un1_lock_count13_i_o2_0_6_1 CFG4 D In - 2.201 - Receiver_0.prbs7_10_0.un1_lock_count13_i_o2_0_6_1 CFG4 Y Out 0.384 2.585 - un1_lock_count13_i_o2_0_6_1 Net - - 0.483 - 1 Receiver_0.prbs7_10_0.un1_lock_count13_i_o2_0_6 CFG4 C In - 3.068 - Receiver_0.prbs7_10_0.un1_lock_count13_i_o2_0_6 CFG4 Y Out 0.196 3.265 - un1_lock_count13_i_o2_0_6 Net - - 0.483 - 1 Receiver_0.prbs7_10_0.un1_lock_count13_i_o2_0 CFG4 D In - 3.748 - Receiver_0.prbs7_10_0.un1_lock_count13_i_o2_0 CFG4 Y Out 0.408 4.156 - N_164 Net - - 0.548 - 2 Receiver_0.prbs7_10_0.un1_lock_count13_i_o2 CFG3 B In - 4.704 - Receiver_0.prbs7_10_0.un1_lock_count13_i_o2 CFG3 Y Out 0.143 4.847 - N_165 Net - - 0.648 - 5 Receiver_0.prbs7_10_0.lock_count_3_i_x2[1] CFG3 C In - 5.495 - Receiver_0.prbs7_10_0.lock_count_3_i_x2[1] CFG3 Y Out 0.200 5.695 - N_81_i Net - - 0.483 - 1 Receiver_0.prbs7_10_0.lock_count_RNO[1] CFG4 C In - 6.178 - Receiver_0.prbs7_10_0.lock_count_RNO[1] CFG4 Y Out 0.200 6.378 - N_14_i_1 Net - - 0.138 - 1 Receiver_0.prbs7_10_0.lock_count[1] SLE D In - 6.516 - ================================================================================================================ Total path delay (propagation time + setup) of 6.738 is 2.402(35.6%) logic and 4.336(64.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Transmitter_0.Replicator_0.reg_tx_val_out IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE Q Replicator_0_tx_val_out 0.094 7.504 Transmitter_0.FIFO_PRBS_0.i[0] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE Q i[0] 0.076 7.715 Transmitter_0.FIFO_PRBS_0.i[1] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE Q i[1] 0.094 7.734 Transmitter_0.prbs7_10_0.tx_count[0] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE Q tx_count[0] 0.076 7.959 Transmitter_0.FIFO_PRBS_0.flag IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE Q flag 0.094 8.049 Transmitter_0.prbs7_10_0.tx_count[1] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE Q tx_count[1] 0.076 8.099 Transmitter_0.FIFO_PRBS_0.data[21] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE Q data[23] 0.076 8.104 Transmitter_0.FIFO_PRBS_0.data[24] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE Q data[26] 0.076 8.104 Transmitter_0.FIFO_PRBS_0.data[27] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE Q data[29] 0.076 8.104 Transmitter_0.FIFO_PRBS_0.data[18] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE Q data[20] 0.076 8.157 =========================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Transmitter_0.FIFO_PRBS_0.reg_data_out[0] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE EN un1_i17_i_0 9.707 7.504 Transmitter_0.FIFO_PRBS_0.reg_data_out[1] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE EN un1_i17_i_0 9.707 7.504 Transmitter_0.FIFO_PRBS_0.reg_data_out[2] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE EN un1_i17_i_0 9.707 7.504 Transmitter_0.FIFO_PRBS_0.reg_data_out[3] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE EN un1_i17_i_0 9.707 7.504 Transmitter_0.FIFO_PRBS_0.reg_data_out[4] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE EN un1_i17_i_0 9.707 7.504 Transmitter_0.FIFO_PRBS_0.reg_data_out[5] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE EN un1_i17_i_0 9.707 7.504 Transmitter_0.FIFO_PRBS_0.reg_data_out[6] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE EN un1_i17_i_0 9.707 7.504 Transmitter_0.FIFO_PRBS_0.reg_data_out[7] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE EN un1_i17_i_0 9.707 7.504 Transmitter_0.FIFO_PRBS_0.reg_data_out[8] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE EN un1_i17_i_0 9.707 7.504 Transmitter_0.FIFO_PRBS_0.reg_data_out[9] IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock SLE EN un1_i17_i_0 9.707 7.504 ================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.707 - Propagation time: 2.202 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.504 Number of logic level(s): 1 Starting point: Transmitter_0.Replicator_0.reg_tx_val_out / Q Ending point: Transmitter_0.FIFO_PRBS_0.reg_data_out[0] / EN The start point is clocked by IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock [rising] on pin CLK The end point is clocked by IGLOO2_Oversampling_top_SERDES_IF_0_SERDES_IF|EPCS_1_TX_CLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- Transmitter_0.Replicator_0.reg_tx_val_out SLE Q Out 0.094 0.094 - Replicator_0_tx_val_out Net - - 0.827 - 5 Transmitter_0.FIFO_PRBS_0.flag_RNIUQIH CFG4 D In - 0.921 - Transmitter_0.FIFO_PRBS_0.flag_RNIUQIH CFG4 Y Out 0.408 1.329 - un1_i17_i_0 Net - - 0.873 - 10 Transmitter_0.FIFO_PRBS_0.reg_data_out[0] SLE EN In - 2.202 - ======================================================================================================== Total path delay (propagation time + setup) of 2.496 is 0.796(31.9%) logic and 1.700(68.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for IGLOO2_Oversampling_top Mapping to part: m2gl010tfbga484-1 Cell usage: AND2 1 use AND3 1 use CCC 2 uses CLKINT 13 uses MSS_010 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SERDESIF_0 1 use SYSRESET 1 use CFG1 9 uses CFG2 212 uses CFG3 227 uses CFG4 513 uses Carry primitives used for arithmetic functions: ARI1 138 uses Sequential Cells: SLE 1010 uses DSP Blocks: 0 I/O ports: 22 I/O primitives: 5 INBUF 2 uses OUTBUF 3 uses Global Clock Buffers: 13 Total LUTs: 1099 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 54MB peak: 165MB) Process took 0h:00m:05s realtime, 0h:00m:04s cputime # Fri Apr 18 09:31:00 2014 ###########################################################]